Memory device and manufacturing method of the same

ABSTRACT

An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film having two impurity regions, a gate electrode, and two wirings connected to the respective impurity regions. The two wirings are insulated from each other by applying a voltage between the gate electrode and at least one of the two wirings to alter the state of the semiconductor film.

TECHNICAL FIELD

The present invention relates to a memory device, and more particularlyto a nonvolatile memory device.

BACKGROUND ART

In modern society, many electronic appliances are used and various datais generated and employed, requiring a memory device to store the data.Various memory devices produced and used today each has differentadvantages and disadvantages, and is selected depending on the data tobe stored and used.

For example, a volatile memory that loses its memory content when thepower is turned off includes a DRAM and an SRAM. The volatile memory haslimited applications because of the volatility; however, it is used as amain memory device or a cash memory of a computer taking advantage of ashort access time. As each memory cell has a small size, alarge-capacity DRAM can be produced easily, though it is controlled in acomplex manner and consumes much power. Meanwhile, an SRAM includes amemory cell constituted by a CMOS and is easily manufactured andcontrolled, though a large-capacity SRAM is produced with difficultysince one memory cell needs six transistors.

A nonvolatile memory that holds its memory content even after the poweris turned off includes: a rewritable memory where data can be rewrittenmany times; a write-once memory where data can be written by a user onlyonce; and a mask ROM where data content is determined in the manufactureof the memory and cannot be rewritten thereafter. As the rewritablememory, there are an EPROM, a flash memory, a ferroelectric memory, andthe like. The EPROM allows an easy writing of data and unit cost per bitis relatively low, though dedicated program device and eraser forwriting and erasing are required. The flash memory and the ferroelectricmemory allow rewriting on a substrate used, have a short access time,and consume low power, though manufacturing steps of a floating gate anda ferroelectric layer are required to increase unit cost per bit.

Each memory cell of a write-once memory is constituted by a fuse, anantifuse, a cross pointer diode, an OLED (Organic Light Emitting Diode),a bistable liquid crystal element, and other devices whose state ischanged by heat or light. In general, a memory device stores data byselecting one of the two states of each memory cell. The write-oncememory device is manufactured with all memory cells having a firststate, and only memory cells specified by a writing operation arechanged to a second state. The change from the first state to the secondstate is irreversible and the changed memory cell cannot be restored.

Manufacturing steps of a write-once memory have limited temperature andmaterials, thus it is not formed on a silicon substrate in many cases.That is, a write-once memory is manufactured in completely differentsteps than a central processing unit (hereinafter referred to as a CPU),an arithmetic circuit, a rectification circuit, a control circuit andthe like (hereinafter collectively referred to as other functionalcircuits to be distinguished from a write-once memory), which aregenerally formed on a silicon substrate. For example, an antifusewrite-once memory has a wiring, an antifuse layer, and a controlelement, which are formed on a plastic or metal substrate (see PatentDocument 1). The memory device manufactured in this manner achieves lowcost, large capacity, low power consumption, and short access time. Inthe case of forming a semiconductor device having a certain function,however, a memory does not operate by itself and other functionalcircuits are necessarily required. Therefore, it is necessary to form amemory such as a write-once memory and other functional circuitsseparately.

In recent years, an IC tag has been known as an example of asemiconductor device where a memory and other functional circuits areintegrated on the same silicon substrate. An IC tag includes memoriessuch as an SRAM, a mask ROM, a flash memory, and a ferroelectric memory.A mask ROM is a memory where data content is determined in themanufacture of the memory and cannot be rewritten by an IC tag user. Inaddition, a piece of data is determined by one photomask; therefore, themask ROM requires as many photomasks as kinds of data. Thus, the maskROM is not practical for cost reasons.

A flash memory and a ferroelectric memory require additional steps forforming a floating gate and a ferroelectric layer in a gate insulatingfilm. Meanwhile, all the circuits other than the memory in an IC tag canbe obtained by CMOS manufacturing steps.

In recent years, technologies for forming a thin film transistor(hereinafter referred to as a TFT) on an insulating substrate have beenactively developed to manufacture a display device such as a liquidcrystal display and an EL display. For example, a driver circuit fordisplaying images and a pixel portion are formed on the same substrateusing TFTs. Since an insulating substrate is not capacitively coupled toa wiring, high speed operation of a circuit can be achieved.Accordingly, various functional circuits such as an arithmetic circuitand a memory circuit are proposed to be formed using TFTs. Anotheradvantage of forming functional circuits on an insulating substrate iscost saving. A glass substrate and a plastic substrate are quiteinexpensive as compared to a silicon substrate. Further, it is possibleto use an insulating substrate with a larger area than a siliconsubstrate that is limited to a small area. Thus, the number of productsmanufactured on an insulating substrate increases than that manufacturedon a silicon substrate, leading to a very inexpensive semiconductordevice.

A memory device formed using TFT manufacturing technologies includes amask ROM, an SRAM, and a flash memory. An SRAM including TFTs can beeasily formed on the same substrate as other functional circuits, thoughit has limited applications because of the volatility. A mask ROM is notpractical since different photomasks are required for different data. Aflash memory requires additional steps for forming a floating gate,though other functional circuits such as an arithmetic circuit on aninsulating substrate can be formed by TFT manufacturing steps.

As set forth above, the invention is made in view of the twotechnologies: a technology for forming a memory device and a technologyfor forming a circuit on an insulating substrate such as a glasssubstrate or an insulating surface.

Patent Document 1

-   Japanese Patent Laid-Open No. 2003-36684

DISCLOSURE OF INVENTION

It is difficult to form a nonvolatile memory and other functionalcircuits on the same substrate with conventional technologies,regardless of whether a semiconductor integrated circuit is formed on asilicon substrate or an insulating substrate. However, when a memory andother functional circuits are formed separately to obtain one device,they are required to be connected externally, which results in increasedsize of a completed device. In addition, at least two circuits that area memory and other functional circuits are expensive to manufacture.Even when a memory and other functional circuits can be formed on thesame substrate as a flash memory and a ferroelectric memory, additionalsteps are required to form the memory. In the manufacture of asemiconductor device, increase in manufacturing steps leads to highcost, limits product specifications, and decreases productivity.

In other words, almost all memory devices manufactured with conventionaltechnologies require specific steps. Accordingly, they cannot be formedon the same substrate as other functional circuits or they requireadditional steps other than TFT manufacturing steps even when formed onthe same substrate as other functional circuits. Such a problem leads toextra cost for a memory in the manufacture of a semiconductor devicehaving a function, for example such as an IC tag.

In view of the foregoing, the invention provides a manufacturing methodof a write-once memory that can be formed by TFT manufacturing stepssimilarly to other functional circuits formed on an insulatingsubstrate. Further, the invention provides an easy-to-use andinexpensive memory device while maintaining product specifications andproductivity even when a memory is formed on the same substrate as otherfunctional circuit.

In view of the foregoing problem, the invention provides a memory devicehaving a write-once memory function by altering a semiconductor filmformed over an insulating substrate such as a glass substrate and aplastic substrate or a substrate having an insulating surface(hereinafter collectively referred to as an insulating substrate).

According to one mode of the invention, a memory device includes amemory cell formed over an insulating surface. The memory cell includesa semiconductor film having two impurity regions, a gate electrode, andtwo wirings connected to the respective impurity regions. Thesemiconductor film is altered by applying a voltage between the gateelectrode and at least one of the two wirings, thereby the two wiringsare insulated from each other.

According to another mode of the invention, a memory device includes afirst memory cell and a second memory cell that are formed over aninsulating surface. Each of the first memory cell and the second memorycell includes a semiconductor film having two impurity regions, a gateelectrode, and two wirings connected to the respective impurity regions.The first memory cell has an insulating state between the two wirings byapplying a voltage between the gate electrode and at least one of thetwo wirings to alter the semiconductor film. The second memory cell hasan initial state. The memory device can have either the insulating stateor the initial state.

According to another mode of the invention, a memory device includes amemory cell formed over an insulating surface. The memory cell includesa semiconductor film having one or two impurity regions, an electrode,and two wirings connected to the respective impurity regions. Thesemiconductor film is altered by applying a voltage between theelectrode and at least one of the two wirings, thereby the two wiringsare insulated from each other.

According to another mode of the invention, a memory device includes afirst memory cell and a second memory cell that are formed over aninsulating surface. Each of the first memory cell and the second memorycell includes a semiconductor film having one or two impurity regions,an electrode, and two wirings connected to the respective impurityregions. The first memory cell has an insulating state between the twowirings by applying a voltage between the electrode and at least one ofthe two wirings to alter the semiconductor film. The second memory cellhas an initial state. When seen from the top of the insulatingsubstrate, the electrode is interposed between the two wirings.

According to the invention, the memory device may include one or moregate electrodes or electrodes.

According to the aforementioned structures, a write-once memory can beformed on an insulating substrate by TFT manufacturing steps. That is,the memory device of the invention can be formed by TFT manufacturingsteps similarly to other functional circuits formed on an insulatingsubstrate, which can suppress an increase in extra cost due toadditional manufacturing steps of a memory. In addition, since a memoryand other functional circuits can be formed by the same steps, thememory does not limit product specifications and not decreaseproductivity.

A glass substrate and a plastic substrate are quite inexpensive ascompared to a silicon substrate. Further, it is possible to use aninsulating substrate with a larger area than a silicon substrate that islimited to a small area. Thus, the number of products manufactured on aninsulating substrate increases than that manufactured on a siliconsubstrate, leading to a very inexpensive semiconductor device.

According to the invention, a write-once memory is formed by TFTmanufacturing steps, thereby an easy-to-use and inexpensive memorydevice can be provided while maintaining product specifications andproductivity even when a memory is formed on the same substrate as otherfunctional circuit.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A and 1B are schematic views showing operations of a memory cellin a memory device of the invention.

FIG. 2 is a diagram showing an example of a memory cell array.

FIGS. 3A to 3E are top plan views and cross sectional views of aresistor.

FIG. 4 is a diagram showing an example of a memory cell array.

FIGS. 5A to 5E are diagrams showing manufacturing steps of a TFT.

FIGS. 6A to 6D are diagrams showing manufacturing steps of a TFT.

FIGS. 7A and 7B are diagrams showing manufacturing steps of a TFT.

FIGS. 8A and 8B are diagrams each showing an application of a memorydevice of the invention.

FIGS. 9A to 9E are diagrams each showing an example of a memory cell ina memory device of the invention.

FIGS. 10A and 10B are photographs showing TFTs of the invention beforeand after being applied a voltage, respectively.

BEST MODE FOR CARRYING OUT THE INVENTION

Although the invention will be described by way of embodiment modes andembodiments with reference to the accompanying drawings, it is to beunderstood that various changes and modifications will be apparent tothose skilled in the art. Therefore, unless such changes andmodifications depart from the scope of the invention, they should beconstrued as being included therein. Note that in all the drawings, thesame components or components having the same function are denoted bythe same reference numerals, and description thereof is omitted.

Embodiment Mode 1

When a voltage higher than required for normal operation of a TFT isapplied between a gate electrode and at least one of two impurityregions (including a high concentration impurity region) of the TFTformed on an insulating substrate, a channel region of the TFT isinsulated. This operation is shown in FIGS. 1A and 1B that are crosssectional views of a TFT before and after being applied a voltagerespectively. For example, a TFT shown in FIG. 1A has a semiconductorfilm 102 formed over an insulating substrate 101, a gate insulating film105 over the semiconductor film 102, and a gate electrode 106 over thegate insulating film 105. The semiconductor film 102 includes two highconcentration impurity regions 103 and a channel region 104. FIG. 1Bshows the TFT after being applied a voltage. In the TFT, at least thechannel region 104 of the semiconductor film 102 is altered and aninsulating region 108 is formed under the gate electrode 106. Then, thegate electrode 106 and the two high concentration impurity regions 103are insulated from each other. The insulating region 108 shown in FIG.1B is a typical example, and it may have various shapes practically.

For example, in a TFT formed on a glass substrate, which has a channellength (hereinafter abbreviated to L) of 4 μm, a channel width(hereinafter abbreviated to W) of 4 μm, and a gate insulating film witha thickness (hereinafter abbreviated to GI) of 20 nm, a voltage of 25 Vis applied between the gate electrode and at least one of the two highconcentration impurity regions for 500 μseconds. Then, the channelregion of the TFT is insulated and the gate electrode and the two highconcentration impurity regions are insulated from each other. Actualphotographs of the TFT before and after being applied a voltage areshown in FIGS. 10A and 10B. FIG. 10A is a photograph of the TFT beforebeing applied a voltage and FIG. 10B is a photograph of the TFT afterbeing applied a voltage, which is seen from the back side of the glasssubstrate.

Alteration in this specification means specifically a change of at leastthe channel region into an insulating state, as from FIG. 10A to FIG.10B, due to a voltage applied to the TFT. It is needless to say that bychanging the voltage application conditions, at least a channel regionof a TFT can be insulated even when the TFT has a different size thanthat shown in FIGS. 10A and 10B. Note that the insulating state means astate where electricity and heat are not conducted.

In this manner, when a voltage higher than required for normal operationof a TFT is applied between a gate electrode and at least one of twoimpurity regions (high concentration impurity regions in this embodimentmode), a current flows through a gate insulating film. The insulatingfilm is made of a highly resistant substance in many cases, and heat isgenerated when a current flows therethrough. When a large amount of heatis generated in a TFT formed on an insulating substrate, the heat cannotescape because of the low thermal conductivity of the insulatingsubstrate, thereby the gate insulating film or a semiconductor film areburned. As a result, the gate electrode and the two high concentrationimpurity regions can be insulated from each other. On the other hand, ina transistor formed on a silicon substrate with high thermalconductivity, heat generated when a current flows through a gateinsulating film does not burn the insulating film and the siliconsubstrate.

According to the experiment in the invention, when a voltage is appliedbetween a gate electrode and at least one of two high concentrationimpurity regions, a channel region is altered to an insulating state noless than 97% of the time, thereby the gate electrode and the two highconcentration impurity regions are insulated from each other, namelythey are brought into a non-conductive state. A defective element isdetected the rest 3% of the time, where a channel region functions as aresistor after being applied a voltage and three terminals are conductedto each other. Defective elements may be caused by dust in asemiconductor film or an insulating film. Therefore, improved accuracyof manufactured TFTs allows defective elements to be further reduced.The generation of defective elements can also be suppressed when a TFThas a double gate structure or a redundant circuit is providedadditionally.

As another defect, two of three terminals that are a gate electrode andtwo wirings connected to an impurity region may be conducted to eachother. The defects such as conduction between three terminals or twoterminals may be caused by excess voltage applied in writing as well asdust. Accordingly, the number of defective elements can be reduced byoptimizing a writing voltage and voltage application time.

A memory device stores data when a memory cell selects one of twostates. The memory device of the invention can store data when a TFT asa memory cell selects one of two states: whether a channel region of theTFT is in an initial state or an insulating state. In a write-oncememory manufactured in the invention, a TFT in the initial state beforebeing applied a voltage has a state ‘1’ while the TFT including achannel region altered to an insulating state by applying a voltage hasa state ‘0’. This relation between states ‘0’ and ‘1’ and the states ofthe TFT is not limited to this, though it is used in this specificationfor convenience.

FIG. 2 is a circuit diagram of a 4-bit memory cell array showing anexample of the memory device of the invention. The memory cell arrayincludes two word lines 201, two bit lines 202, two source lines 204,and four TFTs 206 to 209. The word lines 201, the bit lines 202, and thesource lines 204 are denoted as W0, W1, B0, B1, S0, and S1 respectively.When a voltage of 25 V or higher is applied between a gate electrode andat least one of two impurity regions for 500 μseconds, as set forthabove, each channel region of the TFTs 206 to 209 is altered to aninsulating state.

Described first is an example of a circuit operation for writing ‘0’ tothe TFT 206. The writing operation can be performed by applying avoltage between the gate electrode and at least one of the two impurityregions of the TFT 206. For example, a voltage of 25 V is applied to W0and a voltage of 0 V is applied to B0 and S0 for 500 μseconds. At thistime, it is necessary to determine the voltages of W1, B1 and S1 so that‘0’ is not written to the other TFTs. For example, a voltage of 0 V isapplied to W1 and a voltage of 10 V is applied to B1 and S1. By applyingthese voltages, a voltage of 25 V is applied between the gate electrodeand at least one of the two impurity regions of the TFT 206, thereby thechannel region of the TFT 206 can be insulated.

Brief description is made on the operation of the other TFTs in writing‘0’ to the TFT 206. Since a voltage of 25 V is applied to W0 and avoltage of 10 V is applied to B1 and S1, a voltage of 15 V is appliedbetween the gate electrode and at least one of the two impurity regionsof the TFT 207. However, ‘0’ is not written to the TFT 207 because avoltage of 25 V or higher is not applied thereto. Similarly, ‘0’ is notwritten to the TFT 208 since a voltage of 0 V is applied to W1, B0 andS0. A voltage of 0 V is applied to W1 while a voltage of 10 V is appliedto B0 and S0, therefore, a voltage of 10 V is applied between the gateelectrode and the semiconductor film of the TFT 209, though ‘0’ is notwritten thereto. Note that the voltages applied here are just examples,and a signal can be written only to a selected TFT by arbitrarilydetermining the voltages of each word line 201, bit line 202 and sourceline 204.

Described next is an example of a circuit operation for writing ‘1’ tothe TFT 206. When ‘1’ is written to the TFT 206, no voltage is appliedbetween the gate electrode and at least one of the two impurity regionswhile maintaining the TFT 206 in an initial state. Accordingly, forexample, all the word lines 201, bit lines 202 and source lines 204 mayhave the same voltage so that ‘0’ is not written to the TFT 206. This isjust an example and the potential of each word line 201, bit line 202and source line 204 may be determined by a controlling method of acircuit.

Reading operation of the TFT 206 is described next. The readingoperation determines whether the TFT 206 is in the state ‘1’, namely inthe initial state without being applied a voltage or the TFT 206 is inthe state ‘0’, namely altered to an insulating state. Thus, a voltage ofa threshold or higher is applied to the gate electrode of the TFT 206 todetermine whether a current flows between the two high concentrationimpurity regions. First, before reading, B0 is precharged to 5 V. Then,voltages of 5 V and 0 V are applied to W0 and S0 respectively to readthe potential of B0. At this time, it is necessary to determine thevoltages of W1, B1 and S1 so that the other TFTs are not selected. Forexample, a voltage of 0 V is applied to W1 and S1 so as not to read thepotential of B1. When the TFT 206 is in the state ‘1’ without beingapplied a voltage, the two impurity regions are conducted and a voltageof 0 V is applied to B0 since a voltage of 5 V is applied to W0. On theother hand, when the TFT 206 is applied a voltage and brought into thestate ‘0’, B0 is maintained at 5 V since B0 and S0 are insulated fromeach other. The reading operation of the TFT 206 can thus be performedby applying a voltage equal to or higher than a threshold to W0 andreading a change in the potential of B0.

Brief description is made on the operation of the other TFTs in thereading operation of the TFT 206. Since B1 is not selected to read, thereading operation does not involve the TFT 207 and the TFT 209. The TFT208 does not change the potential of the bit line since W0 has a voltageof 0 V. Therefore, the other TFTs do not influence the reading operationof the TFT 206.

As set forth above, in this embodiment mode, a memory cell has twostates: switching state and insulating state. Thus, a memory cell can beconstituted by only one TFT, leading to reduced area of a memory cellarray and increased memory capacity.

Embodiment Mode 2

In a memory device of the invention, a high concentration impurity maybe added over the entire surface of a semiconductor film of TFT as amemory cell. Instead, an impurity may be added to any portion of asemiconductor film and two wirings may be connected thereto; however,when forming an impurity region arbitrarily, the element does notfunction as a transistor. Meanwhile, when a high concentration impurityis added over the entire surface of a semiconductor film, all the threeterminals can be insulated from each other by applying a voltage betweenan electrode and at least one of two wirings.

Described in this embodiment mode is an example where one impurityregion (high concentration impurity region in this embodiment mode) isformed over a semiconductor film on an insulating substrate and twowirings are connected to the semiconductor film with one electrodeinterposed therebetween. FIGS. 3A and 3C are top plan views of anelement having such a structure. FIGS. 3B, 3D, and 3E are crosssectional views of an element having such a structure. FIGS. 3A and 3Bshow a normal TFT where a high concentration impurity is added to asemiconductor film before forming a gate electrode on an insulatingfilm. FIGS. 3C, 3D, and 3E show a TFT including a void 307 with anarbitrary width in a gate electrode, where a high concentration impurityis added to a semiconductor film after forming the electrode. The widthof the void 307 should be determined so that the two wirings areinsulated when applying a voltage between the electrode and thesemiconductor film. Both the elements shown in FIGS. 3A and 3C have thetwo wirings conducted through the high concentration impurity region ofthe semiconductor film, thus these elements are referred to as resistorelements in this specification to be distinguished from TFTs.

In each of the resistor elements shown in FIGS. 3A to 3E, asemiconductor film 301 is formed over an insulating substrate 303, aninsulating film 305 is formed over the semiconductor film 301, and anelectrode 302 is formed over the insulating film 305. Two wirings 306are connected to a high concentration impurity region 304 in thesemiconductor film 301. The high concentration impurity region 304 inthe semiconductor film 301 and the wirings 306 connected to thesemiconductor film 301 may be formed anywhere as long as the electrode302 is formed between the two wirings 306. The form of the electrode 302can also be determined arbitrarily as shown in FIG. 3C where the void307 with an arbitrary width is formed in the gate electrode. Further,the form of the resistor element can be arbitrarily determined as well,and FIGS. 3A to 3E show just examples.

For example, the resistor element shown in FIG. 3A has an L of 4 μm, a Wof 4 μm, and a GI of 20 nm, and a voltage of 25 V is applied between theelectrode and at least one of the two wirings for 500 μseconds similarlyto Embodiment Mode 1. Then, the electrode and the two wirings areinsulated from each other. Needless to say, even when the element has adifferent size than that shown here, the three terminals can beinsulated from each other by changing the voltage applicationconditions. In this embodiment mode, a write-once memory is manufacturedutilizing such a structure.

FIG. 4 is a circuit diagram of a 4-bit memory cell array showing anexample of this embodiment mode. The memory cell array includes two wordlines 31, two bit lines 32, two selection control lines 33, fourresistor elements 34, and four selection transistors 35. The word lines31, the bit lines 32 and the selection control lines 33 are denoted asW0, W1, B0, B1, W′0, and W′1 respectively. A memory cell 22 is selectedby W0 and B0, a memory cell 24 is selected by W0 and B1, a memory cell42 is selected by W1 and B0, and a memory cell 44 is selected by W1 andB1. Similarly to the example shown in FIGS. 3A and 3B, an electrode andtwo impurity regions of the resistor element 34 are insulated from eachother when applying a voltage of 25 V or higher between the electrodeand at least one of the two impurity regions. Note that in thisembodiment mode, the impurity region may be formed over the entiresurface of the semiconductor film, thus a voltage is applied between theelectrode and the semiconductor film.

Described first is an example of a circuit operation for writing ‘0’ tothe memory cell 22. The writing operation can be performed by applying avoltage between the electrode and the semiconductor film, namely atleast one of the two wirings connected to the semiconductor film of theresistor element 34 in the memory cell 22. For example, a voltage of 25V is applied to W0 and a voltage of 0 V is applied to B0 and W′0 for 500μseconds. At this time, it is necessary to determine the voltages of W1,B1 and W′1 so that ‘0’ is not written to the other resistor elements.For example, a voltage of 0 V is applied to W1 and W′1 and a voltage of10 V is applied to B1. By applying these voltages, a voltage of 25 V canbe applied between the electrode and the semiconductor film of theresistor element 34 in the memory cell 22, thereby the electrode and thetwo wirings can be insulated from each other. The applied voltages shownhere are just examples and the writing operation can be performed byother conditions as well.

Brief description is made on the operation of the other memory cells inwriting ‘0’ to the memory cell 22. Since a voltage of 25 V is applied toW0, a voltage of 10 V is applied to B1, and a voltage of 0 V is appliedto W′0, a voltage of 15 V is applied between the electrode and thesemiconductor film of the memory cell 24. However, ‘0’ is not written tothe memory cell 24 because a voltage of 25 V or higher is not appliedthereto. Similarly, ‘0’ is not written to the memory cell 42 since avoltage of 0 V is applied to W1, W′1 and B0. A voltage of 0 V is appliedto W1 and W′1 while a voltage of 10 V is applied to B0, therefore, avoltage of 10 V is applied between the electrode and the semiconductorfilm of the memory cell 44, though ‘0’ is not written thereto. In thismanner, ‘0’ can be written only to a selected memory cell by arbitrarilydetermining the voltages of the word lines 31, the bit lines 32 and theselection control lines 33.

Described next is an example of a circuit operation for writing ‘1’ tothe memory cell 22. When ‘1’ is written to the memory cell 22, novoltage is applied between the electrode and the semiconductor film ofthe resistor element 34 while maintaining the memory cell 22 in aninitial state. Accordingly, for example, all the word lines 31, bitlines 32 and selection control lines 33 may have the same voltage suchas 0 V so that ‘0’ is not written to the memory cell 22. This is just anexample and the potential of each word line 31, bit line 32 andselection control line 33 may be determined arbitrarily by a controllingmethod of a circuit.

Reading operation of the memory cell 22 is described next. The readingoperation determines whether the resistor element 34 in the memory cell22 is in the state ‘1’, namely in the initial state without beingapplied a voltage or the resistor element 34 is applied a voltage and inthe state ‘0’, namely altered to an insulating state. Thus, a voltage ofa threshold or higher is applied to the gate electrode of the selectiontransistor 35 in the memory cell 22 to determine whether B0 is conductedto a ground of the two high concentration impurity regions of theselection transistor 35. First, before reading, B0 is precharged to 5 V.Then, a voltage of 5 V is applied to W′0. At this time, it is necessaryto determine the voltages of W′1 and B1 so that the other transistorsare not selected. W0 and W1 are used only in the writing operation andare not required in the reading operation. For example, a voltage of 0 Vis applied to W′1 so as not to read the potential of B1. When theresistor element 34 in the memory cell 22 is in the state ‘1’, namely inthe initial state without being applied a voltage, B0 is conducted tothe ground and a voltage of 0 V is applied to B0. On the other hand,when the resistor element 34 in the memory cell 22 is applied a voltageand brought into the state ‘0’, namely in the insulating state, B0 ismaintained at 5 V even when a voltage of 5 V is applied to W0 since B0is insulated from the ground. The reading operation of the memory cell22 can thus be performed by applying a voltage to W′0 and reading achange in the potential of B0.

Brief description is made on the operation of the other memory cells inthe reading operation of the memory cell 22. Since B1 is not selected toread, the reading operation does not involve the memory cell 24 and thememory cell 44. The memory cell 42 does not change the potential of thebit line since W′0 has a voltage of 0 V. Therefore, the other memorycells do not influence the reading operation of the memory cell 22.

In this embodiment mode, each memory cell includes the two elements,which increases the area of the memory cell array. In such a case,however, an element using a high voltage in writing (e.g., a decoderconnected to W0 or W1) and an element using a low voltage in reading(e.g., a decoder connected to W′0 or W′1) can be formed separately. Whenusing a high voltage, a TFT is required to have a large L to withstand ahigh voltage. However, the TFT having a large L is not suitable for highspeed operation, thus a TFT using a low voltage generally has a small L.Accordingly, it is very advantageous that the elements are formedseparately for high speed operation and easy operation control. In thisembodiment mode, a TFT can be used instead of the resistor element 34and a memory TFT and a selection TFT can be formed separately in amemory cell.

EMBODIMENT Embodiment 1

In this embodiment, a manufacturing method of a TFT on a glass substrateis specifically described with reference to FIGS. 5A to 5E, FIGS. 6A to6D and FIGS. 7A and 7B. Description is made with reference to crosssectional views of an N-channel TFT and a P-channel TFT.

First, a peeling layer 501 is formed over a substrate 500 (FIG. 5A). Inthis embodiment, an a-Si film (amorphous silicon film) with a thicknessof 50 nm is formed over a glass substrate (e.g., a 1737 substrate,product of Corning Incorporated) by low pressure CVD. As for thesubstrate 500, a quartz substrate, a substrate made of an insulatingmaterial such as alumina, a silicon wafer substrate, a plastic substratehaving enough heat resistance to the treatment temperature in thesubsequent step, and the like may be employed as well as the glasssubstrate. The peeling layer 501 is preferably formed of a film mainlycontaining silicon such as polycrystalline silicon, single crystallinesilicon and SAS (semi-amorphous silicon that is also referred to asmicrocrystalline silicon) as well as amorphous silicon, though theinvention is not limited to these. The peeling layer 501 may be formedby plasma CVD or sputtering as well as low pressure CVD. A film dopedwith an impurity such as phosphorous may be employed as well. Thethickness of the peeling layer 501 is desirably 50 to 60 nm, though itmay be 30 to 50 nm in the case of employing an SAS.

Next, a protective film 502 (also referred to as a base film or a baseinsulating film) is formed over the peeling layer 501 (FIG. 5A). In thisembodiment, the protective film 502 has a three-layer structure where aSiON film with a thickness of 100 nm, a SiNO film with a thickness of 50nm, and a SiON film with a thickness of 100 nm are stacked in this orderfrom the substrate side, though the material, the thickness, and thenumber of layers are not limited to these. For example, instead of theSiON film on the bottom layer, a heat resistant resin such as siloxanewith a thickness of 0.5 to 3 μm may be formed by spin coating, slitcoating, droplet discharging, or the like. Alternatively, a siliconnitride film (SiN, Si₃N₄ or the like) may be employed. The thickness ofeach layer is preferably in the range of 0.05 to 3 μm and can beselected within this range as required. A silicon oxide film can beformed by thermal CVD, plasma CVD, atmospheric pressure CVD, biasECRCVD, or the like using a mixed gas of SiH₄ and O₂, TEOS (tetraethoxysilane) and O₂, or the like. A silicon nitride film can be typicallyformed by plasma CVD using a mixed gas of SiH₄ and NH₃. A SiON film or aSiNO film can be typically formed by plasma CVD using a mixed gas ofSiH₄ and N₂O.

Subsequently, TFTs are formed over the protective film 502. Note thatother thin film active elements such as organic TFTs and thin filmdiodes may be formed as well as the TFTs. In order to form a TFT, first,an island shape semiconductor film 503 is formed over the protectivefilm 502 (FIG. 5B). The island shape semiconductor film 503 is formedusing an amorphous semiconductor, a crystalline semiconductor or asemi-amorphous semiconductor, which mainly contains silicon, silicongermanium (SiGe), or the like. Note that if a material mainly containingsilicon such as a-Si is employed for the peeling layer 501 and theisland shape semiconductor film 503, the protective film 502 that is incontact with them may be formed using SiO_(x)N_(y) in view of theadhesiveness. In this embodiment, an amorphous silicon film with athickness of 70 nm is formed and the surface thereof is treated with asolution containing nickel. Thermal crystallization is performed at atemperature of 500 to 750° C. so that a crystalline siliconsemiconductor film is obtained. Then, the crystallinity thereof may beimproved by laser crystallization. Note that the film may be formed byplasma CVD, sputtering, LPCVD, or the like. As a crystallizing method,laser crystallization, thermal crystallization, or thermalcrystallization using a catalyst other than nickel (Fe, Ru, Rh, Pd, Os,Ir, Pt, Cu, Au, or the like) may be adopted, or such methods may beperformed alternately a plurality of times.

Alternatively, the semiconductor film having an amorphous structure maybe crystallized by a continuous wave laser. In order to obtain a crystalwith a large grain size during crystallization, a solid state lasercapable of continuous wave may be used and it is preferable to applysecond to fourth harmonics of a fundamental wave (the crystallization inthis case is referred to as CWLC). Typically, a second harmonic (532 nm)or a third harmonic (355 nm) of a Nd:YVO₄ laser (a fundamental wave:1064 nm) is applied. When a continuous wave laser is used, laser lightemitted from a continuous wave YVO₄ laser having an output of 10 W isconverted into a harmonic by a non-linear optical element. There is alsoa method for emitting a harmonic by putting a YVO₄ crystal or a GdVO₄crystal and a non-linear optical element in a resonator. Then, the laserlight is preferably formed in a rectangular shape or an ellipse shape atan irradiated surface with an optical system to irradiate a subject. Inthat case, an energy density of about 0.01 to 100 MW/cm² (preferably 0.1to 10 MW/cm²) is required. Then, the semiconductor film is preferablyirradiated with laser light while being moved relatively to the laserlight at a speed of about 10 to 2000 cm/sec.

When a pulsed laser is used, a pulsed laser having a frequency band ofseveral tens to several hundreds Hz is generally used, though a pulsedlaser having an extremely higher oscillation frequency of 10 MHz orhigher may be used as well (the crystallization in this case is referredto as MHzLC). It is said that it takes several tens to several hundredsnsec to solidify a semiconductor film completely after the semiconductorfilm is irradiated with the pulsed laser light. When the pulsed laserlight has an oscillation frequency of 10 MHz or higher, it is possibleto irradiate the next pulsed laser light before the semiconductor filmis solidified after it is melted by the previous laser light. Therefore,unlike the case of the conventional pulsed laser, the interface betweenthe solid phase and the liquid phase can be moved continuously in thesemiconductor film, and thus the semiconductor film having a crystalgrain grown continuously along the scanning direction can be formed.More specifically, it is possible to form an aggregation of crystalgrains each of which has a width of 10 to 30 μm in the scanningdirection and a width of about 1 to 5 μm in the direction perpendicularto the scanning direction. By forming such single crystal grainsextending long in the scanning direction, a semiconductor film havingfew crystal grain boundaries at least in the channel direction of theTFT can be formed. Note that when the protective film 502 is partiallyformed using siloxane that is a heat resistant organic resin, heat leakfrom the semiconductor film can be prevented in the aforementionedcrystallization, leading to effective crystallization.

The crystalline silicon semiconductor film is obtained through theaforementioned steps. The crystals thereof are preferably aligned in thesame direction as the source, channel and drain direction. The thicknessof the crystalline layer thereof is preferably 20 to 200 nm (typically40 to 170 nm, and more preferably 50 to 150 nm). Subsequently, anamorphous silicon film for gettering of a metal catalyst is formed overthe semiconductor film with an oxide film interposed therebetween, andheat treatment is performed at a temperature of 500 to 750° C. forgettering. Furthermore, in order to control a threshold value as a TFTelement, boron ions are injected into the crystalline siliconsemiconductor film at a dosage of 10¹³/cm². Then, etching is performedwith a resist used as a mask to form the island shape semiconductor film503. Alternatively, the crystalline semiconductor film may be obtainedby forming a polycrystalline semiconductor film directly by LPCVD (LowPressure CVD) using a source gas of disilane (Si₂H₆) and germaniumfluoride (GeF₄). The flow rate of the gas is such thatSi₂H₆/GeF₄=20/0.9, the temperature for forming the film is 400 to 500°C., and He or Ar is used as a carrier gas, though the invention is notlimited to these conditions.

A TFT, particularly the channel region thereof is preferably added withhydrogen or halogen of 1×10¹⁹ to 1×10²² cm³, and more preferably 1×10¹⁹to 5×10²⁰ cm⁻³. In the case of using an SAS, it is preferably added withhydrogen or halogen of 1×10¹⁹ to 2×10²¹ cm⁻³. In either case, it isdesirable that the amount of hydrogen or halogen be larger than thatcontained in silicon single crystals used for an IC chip and the like.According to this, local cracks that may be generated at the TFT portioncan be terminated by hydrogen or halogen.

Then, a gate insulating film 504 is formed over the island shapesemiconductor film 503 (FIG. 5B). The gate insulating film 504 ispreferably formed of a single layer or stacked layers of a filmcontaining silicon nitride, silicon oxide, silicon nitride oxide, orsilicon oxynitride by a thin film forming method such as plasma CVD andsputtering. In the case of the stacked layers, a three-layer structuremay be adopted for example, where a silicon oxide film, a siliconnitride film and a silicon oxide film are stacked in this order from thesubstrate side.

Subsequently, a gate electrode 505 is formed (FIG. 5C). In thisembodiment, Si and W (tungsten) are stacked by sputtering, and etchedwith a resist 506 used as a mask to form the gate electrode 505.Needless to say, the material, the structure and the forming method ofthe gate electrode 505 are not limited to these and can be selectedappropriately. For example, a stacked structure of Si and NiSi (NickelSilicide) doped with an N-type impurity, or a stacked structure of TaN(tantalum nitride) and W (tungsten) may be employed. Alternatively, thegate electrode 505 may be formed of a single layer employing anyconductive material. A mask of SiO_(x) or the like may be used insteadof the resist mask. In this case, a patterning step of the mask such asSiO_(x) and SiON (such a mask made of an inorganic material is referredto as a hard mask) is additionally required, while the mask film is lessdecreased in etching as compared with the resist, thereby a gateelectrode layer with a desired width can be formed. Alternatively, thegate electrode 505 may be selectively formed by droplet dischargingwithout using the resist 506. As for the conductive material, variouskinds of materials can be selected depending on the function of theconductive film. When the gate electrode and an antenna aresimultaneously formed, the material may be selected in consideration oftheir functions. As an etching gas for etching the gate electrode, amixed gas of CF₄, Cl₂ and O₂, or a Cl₂ gas is employed here, though theinvention is not limited to this.

Subsequently, a resist 509 is formed so as to cover portions to beP-channel TFTs 507. An N-type impurity element 510 (typically, P(phosphorous) or As (arsenic)) is doped to the island shapesemiconductor films of N-channel TFTs 508 at a low concentration withthe gate electrode used as a mask (a first doping step, FIG. 5D). Thefirst doping step is performed under such conditions as a dosage of1×10¹³ to 6×10¹³/cm² and an accelerated voltage of 50 to 70 keV, thoughthe invention is not limited to these conditions. In the first dopingstep, through doping is performed through the gate insulating film 504to form a couple of low concentration impurity regions 511. Note thatthe first doping step may be performed to the entire surface withoutcovering the P-channel TFT regions with the resist 509.

After the resist 509 is removed by ashing or the like, another resist512 is formed so as to cover the N-channel TFT regions. A P-typeimpurity element 513 (typically, B (boron)) is doped to the island shapesemiconductor films of the P-channel TFTs 507 at a high concentrationwith the gate electrode used as a mask (a second doping step, FIG. 5E).The second doping step is performed under such conditions as a dosage of1×10¹⁶ to 3×10¹⁶/cm² and an accelerated voltage of 20 to 40 keV. In thesecond doping step, through doping is performed through the gateinsulating film 504 to form a couple of P-type high concentrationimpurity regions 514.

After the resist 512 is removed by ashing or the like, an insulatingfilm 601 is formed over the entire surface of the substrate (FIG. 6A).In this embodiment, a SiO₂ film with a thickness of 100 nm is formed byplasma CVD. Then the entire surface of the substrate is covered with aresist 602, and resist 602, the insulating film 601 and the gateinsulating film 504 are removed by etch back to form a sidewall 603 in aself-aligned manner (FIG. 6B). As an etching gas, a mixed gas of CHF₃and He is employed. Note that if the insulating film 601 is formed onthe back side of the substrate as well, the insulating film on the backside is etched and removed with the resist 602 used as a mask (this stepis called a back side treatment).

The forming method of the sidewall 603 is not limited to theaforementioned one. For example, methods shown in FIGS. 7A and 7B may beemployed as well. FIG. 7A shows an insulating film 701 having a two ormore layer stacked structure. The insulating film 701 has, for example,a two-layer structure of a SiON (silicon oxynitride) film with athickness of 100 nm and an LTO (Low Temperature Oxide) film with athickness of 200 nm. In this embodiment, the SiON film is formed byplasma CVD, and the LTO film is formed by low pressure CVD using a SiO₂film. Then, etch back is performed with the resist 602 used as a mask,thereby forming the sidewall 603 having an L shape and an arc shape.FIG. 7B shows the case where etching is performed so that the insulatingfilm 702 is not removed by the etch back. The insulating film 702 inthis case may be formed of a single layer or stacked layers. Thesidewall 603 serves as a mask when an N-type impurity is doped at a highconcentration in the subsequent step to form a low concentrationimpurity region or a non-doped offset region under the sidewall 603. Inany of the aforementioned forming methods of the sidewall, theconditions of the etch back may be changed depending on the width of thelow concentration impurity region or the offset region to be formed.

In the semiconductor device of the invention, the memory cell operatesnormally without sidewalls. Therefore, in FIG. 6B and thereafter, thetwo TFTs on the left side have side walls and the two TFTs on the rightside does not have side walls.

Subsequently, another resist 604 is formed so as to cover the P-channelTFT regions. An N-type impurity element 605 (typically, P or As) isdoped at a high concentration with the gate electrode 505 and thesidewall 603 used as masks (a third doping step, FIG. 6C). The thirddoping step is performed under such conditions as a dosage of 1×10¹³ to5×10¹⁵/cm² and an accelerated voltage of 60 to 100 keV. In the thirddoping step, a couple of N-type high concentration impurity regions 606are formed. After the resist 604 is removed by ashing or the like,thermal activation of the impurity regions may be performed. Forexample, a SiON film with a thickness of 50 nm is formed, and then heattreatment is performed at a temperature of 550° C. for four hours in anitrogen atmosphere. Alternatively, it is also possible that a SiN_(x)film containing hydrogen is formed to have a thickness of 100 nm andheat treatment is performed at a temperature of 410° C. for one hour ina nitrogen atmosphere. According to this, defects in the crystallinesemiconductor film can be improved. This step enables to, for example,terminate a dangling bond in the crystalline silicon and is called ahydrotreatment step. Then, a SiON film with a thickness of 600 nm isformed as a cap insulating film for protecting the TFT. Note that theaforementioned hydrotreatment step may be performed after the formationof this SiON film. In that case, a SiN_(x) film and a SiON film thereonmay be continuously formed. In this manner, the insulating film includesthree layers of SiON, SiN_(x) and SiON that are stacked in this orderfrom the substrate side over the TFT, though the structure and thematerial are not limited to these. Note that such an insulating film ispreferably formed, since it also has a function to protect the TFT.

Subsequently, an interlayer film 607 is formed over the TFT (FIG. 6D).For the interlayer film 607, a heat resistant organic resin such aspolyimide, acrylic, polyamide, and siloxane may be employed. Theinterlayer film 607 may be formed by spin coating, dipping, sprayapplication, droplet discharging (inkjet printing, screen printing,offset printing or the like), a doctor knife, a roll coater, a curtaincoater, a knife coater, or the like depending on the material thereof.Alternatively, an inorganic material may be employed such as a film ofsilicon oxide, silicon nitride, silicon oxynitride, PSG (phosphosilicateglass), BPSG (boron phosphosilicate glass), and alumina. Theseinsulating films may also be stacked to form the interlayer film 604. Aprotective film 608 may be formed over the interlayer film 607. As theprotective film 608, a film containing carbon such as DLC (Diamond LikeCarbon) and carbon nitride (CN), a silicon oxide film, a silicon nitridefilm, a silicon nitride oxide film, or the like may be employed. Theprotective film 608 may be formed by plasma CVD, atmospheric pressureplasma, or the like. Alternatively, a photosensitive ornonphotosensitive organic material such as polyimide, acrylic,polyamide, resist, and benzocyclobutene, or a heat resistant organicresin such as siloxane may be employed. A filler may be mixed into theinterlayer film 607 or the protective film 608 in order to prevent thesefilms from being detached or cracked due to stress generated by adifference of thermal expansion coefficients between the interlayer film607 or the protective film 608 and a conductive material or the like ofa wiring that is formed later.

After forming a resist, etching is performed to form contact holes, sothat a wiring 609 is formed (FIG. 6D). As an etching gas for forming thecontact holes, a mixed gas of CHF₃ and He is employed, though theinvention is not limited to this. The wiring 609 is formed by sputteringand patterning so as to have a five-layer structure where Ti, TiN,Al—Si, Ti, and TiN are stacked in this order from the substrate side. Bymixing Si into the Al layer, hillock can be prevented from generating inthe resist baking when the wiring is patterned. Instead of Si, Cu ofabout 0.5% may be mixed. When the Al—Si layer is sandwiched between Tiand TiN, hillock resistance can be further improved. In the patterning,the aforementioned hard mask of SiON or the like is preferably employed.Note that the material and the forming method of the wirings are notlimited to these, and the aforementioned material for forming the gateelectrode may be employed as well.

Through the aforementioned steps, a semiconductor device having TFTs iscompleted. The semiconductor device includes an IC tag, an IC chip, awireless chip, and the like. Although a top gate structure is employedin this embodiment, a bottom gate structure (an inversely staggeredstructure) may be employed as well. A region where a thin film activeelement such as a TFT is not formed mainly includes a base insulatingfilm material, an interlayer insulating film material and a wiringmaterial. This region preferably occupies 50% or more, and morepreferably 70 to 95% of the whole semiconductor device. Meanwhile, it ispreferable that an island shape semiconductor region (island) of theactive element including the TFT portion occupy 1 to 30%, and morepreferably 5 to 15% of the whole semiconductor device. As shown in FIG.6D, the thickness of the protective film or the interlayer film in thesemiconductor device is desirably controlled so that the distance(t_(over)) between the an semiconductor layer of the TFT and the lowerprotective film may be the same or substantially the same as thedistance (t_(over)) between the semiconductor layer and the upperinterlayer film (or protective film if formed). By disposing thesemiconductor layer in the middle of the semiconductor device in thismanner, stress applied to the semiconductor layer can be alleviated,thereby generation of cracks can be prevented.

Embodiment 2

Described in this embodiment is an example of a semiconductor deviceincorporating the memory device of the invention on the same substrate.An IC tag can be taken as an example of the semiconductor device where amemory and other functional circuits are integrated on the samesubstrate. FIG. 8A is a block diagram of an IC tag. An IC tag 801includes an RF circuit 802, a power supply circuit 803, a commandcontrol circuit 804, a clock 805, a congestion control circuit 806, amemory control circuit 807, a memory 808, and an antenna 809. Thesefunctional circuits are formed on the same insulating substrate. Notethat the antenna 809 may be formed on the same substrate or providedexternally and connected to a terminal formed on the same substrate,thus the antenna 809 is surrounded by a dashed line in the drawing.

In the IC tag 801, all the circuits except for the memory 808 can beformed by the TFT manufacturing steps. When the memory device of theinvention is incorporated in the memory 808, all the circuits can beformed by the same manufacturing steps. In the case where thesemiconductor device is formed on one substrate as shown in thisembodiment, improved productivity and cost saving can be achieved byforming all the circuits by the same manufacturing steps.

A write-once memory can be suitably applied to the IC tag because,similarly to a bar code, it is not necessary to change the data contentof a memory once it is determined. The security of an IC tag that isused for individual recognition and goods management can be improved bypreventing the data content from being rewritten. Further, the IC tagshould hold data for a long period; therefore, a write-once memoryperforming an irreversible operation for writing data is suitablyincorporated in the IC tag. In addition, if data should be writtenduring the use of the IC tag, available memory can be reserved asneeded. In this manner, by incorporating the memory device of theinvention in the IC tag, high-security and easy-to-use product can beprovided.

An IC tag operates with a semiconductor device formed on an insulatingsubstrate. The memory device of the invention can be used as a part of adevice. An example of this case is shown in FIG. 8B. A home electronicappliance 810, for example such as a rice cooker and an air conditioner,includes a CPU 812, a memory 811, an I/O controller 813, and an externaldevice 814. The memory 811 incorporated in this electronic appliance isa program ROM where operating data of the appliance is written beforeshipment thereof.

The CPU 812, the memory 811 and the I/O controller 813 are generallyformed as individual ICs; however, they can be formed on the sameinsulating substrate using TFTs. It is very advantageous that thecircuits are formed on the same substrate even for a part of theappliance as shown in this embodiment. For example, when the CPU 812,the memory 811 and the I/O controller 813 are formed as individual ICs,they are connected to each other with external wirings. Meanwhile, whenthey are formed on the same substrate, external connecting wirings areno longer required, leading to significantly reduced size of theproduct. Further, steps and cost for connection are reduced, whichresults in cost saving of the product.

Since the operating data written to the memory is not required to berewritten after shipment of the product, a write-once memory is suitablyapplied to the electronic appliance. In addition, the data can bewritten easily, therefore, the data content can be determined andwritten at the last stage of the manufacture of the product taking intoconsideration a change or update of the written data.

Embodiment 3

Described in this embodiment are measures for reducing writing defectsof a memory cell. Description is made with reference to FIGS. 9A and 9Cshowing top plan views of a TFT. Description is made with reference toFIGS. 9B, 9D, and 9E showing cross sectional views of a TFT. A TFTincludes a semiconductor film 901 formed over an insulating substrate903, a gate insulating film 905 over the semiconductor film 901, and agate electrode 902 over the gate insulating film 905. The semiconductorfilm 901 has high concentration impurity regions 904 to which twowirings 906 are connected respectively. The memory cell in the memorydevice of the invention may have a writing defect 907 as shown in FIGS.9A and 9B. When a voltage is applied between a gate electrode and asemiconductor film, three terminals of a TFT are generally insulatedfrom each other; however, in a defective element, the semiconductor film901 and the gate insulating film 905 function as a resistor and thethree terminals are conducted to each other.

As a measure for preventing such a defective element, it is suggestedthat a TFT adopt a double gate structure having two gate electrodes asshown in FIGS. 9C and 9D. A defective element is generated at randomsince it is supposedly caused by dust in a semiconductor film or aninsulating film. Even when the defect 907 occurs in one channel regionof the two gate electrodes as shown in FIG. 9E, for example, the twowirings 906 are insulated if the other channel region becomes aninsulating region 908, therefore, the TFT can be used as a normal memorycell. Specifically, according to the present data, a defective elementis detected about 3% of the time. Since the defective element isgenerated at random, if a double gate structure is adopted, thegeneration can be probabilistically reduced to 0.1% or less.

By applying the aforementioned measure, a TFT may have a multi-gatestructure to reduce a defective element. The multi-gate here means twoor more gate electrodes in a TFT. The generation of defective elementscan be reduced with the increase in the number of gate electrodes in aTFT. The number of gate electrodes is desirably optimized taking intoconsideration current consumption or applied voltage during the use of amemory, the area of a memory cell array, and the like.

A defective element is still generated with the increase in memorycapacity. In such a case, a redundant circuit can be additionallyprovided similarly to a memory device manufactured today. Alternatively,by controlling an external circuit, access to the defective element canbe prohibited as a flash memory.

EXPLANATION OF REFERENCE

22: memory cell 24: memory cell 31: word line 32: bit line 33: selectioncontrol line 34: resistor element 35: selection transistor 42: memorycell 44: memory cell 100: TFT 101: insulating substrate 102:semiconductor film 103: high concentration impurity region 104: channelregion 105: gate insulating film 106: gate electrode 107: TFT 108:insulating region 201: word line 202: bit line 203: TFT 204: source line206: TFT 207: TFT 208: TFT 209: TFT 301: semiconductor film 302:electrode 303: insulating substrate 304: high concentration impurityregion 305: insulating film 306: wiring 307: void 500: substrate 501:peeling layer 502: protective film 503: island shape semiconductor film504: gate insulating film 505: gate electrode 506: resist 507: P-channelTFT 508: N-channel TFT 509: resist 510: impurity element 511: lowconcentration impurity region 512: resist 513: impurity element 514:high concentration impurity region 601: insulating film 602: resist 603:side wall 604: resist 605: impurity element 606: high concentrationimpurity region 607: interlayer film 608: protective film 609: wiring701: insulating film 702: insulating film 801: IC tag 802: RF circuit803: power supply circuit 804: command control circuit 805: clock 806:congestion control circuit 807: memory control circuit 808: memory 809:antenna 810: electronic appliance 811: memory 812: CPU 813: I/Ocontroller 814: external device 901: semiconductor film 902: gateelectrode 903: insulating substrate 904: high concentration impurityregion 905: gate insulating film 906: wiring 907: defect 908: insulatingregion

The invention claimed is:
 1. A write-once memory device comprising: afirst memory cell formed over an insulating surface, and comprising afirst semiconductor film having at least two first impurity regions anda first region therebetween, a first insulating film over the firstsemiconductor film, a first gate electrode formed over the first region,and at least two first wirings connected to the respective firstimpurity regions; and a second memory cell formed over the insulatingsurface, and comprising a second semiconductor film having at least twosecond impurity regions and a second region therebetween, a secondinsulating film over the second semiconductor film, a second gateelectrode formed over the second region, and at least two second wiringsconnected to the respective second impurity regions, wherein the firstregion is altered to an insulating state and the second region ismaintained in an initial state when applying a gate voltage to the firstgate electrode and the second gate electrode, a first voltage to atleast one of the two first wirings, and a second voltage to at least oneof the two second wirings, and wherein the first voltage is lower thanthe second voltage.
 2. The write-once memory device according to claim1, further comprising sidewalls formed on side surfaces of the firstgate electrode.
 3. The write-once memory device according to claim 1,further comprising sidewalls formed on side surfaces of the second gateelectrode.
 4. The write-once memory device according to claim 1, furthercomprising sidewalls formed on side surfaces of each of the first gateelectrode and the second gate electrode.
 5. A write-once memory devicecomprising: a first memory cell formed over an insulating surface, andcomprising a first semiconductor film comprising at least three firstimpurity regions, a first region, and a second region, a firstinsulating film over the first semiconductor film, a first gateelectrode formed over the first region, a second gate electrode formedover the second region, and at least two first wirings connected to therespective first impurity regions, and a second memory cell formed overthe insulating surface, and comprising a second semiconductor filmcomprising at least three second impurity regions, a third region, and afourth region, a second insulating film over the second semiconductorfilm, a third gate electrode formed over the third region, a fourth gateelectrode formed over the fourth region, and at least two second wiringsconnected to the respective second impurity regions, wherein the firstregion is altered to an insulating state and the third region ismaintained in an initial state when applying a gate voltage to the firstgate electrode and the third gate electrode, a first voltage to at leastone of the two first wirings, and a second voltage to at least one ofthe two second wirings, wherein the first voltage is lower than thesecond voltage, wherein each of the first region and the second regionis formed between the first impurity regions, and wherein each of thethird region and the fourth region is formed between the second impurityregions.
 6. The write-once memory device according to claim 5, furthercomprising sidewalls formed on side surfaces of the first gateelectrode.
 7. The write-once memory device according to claim 5, furthercomprising sidewalls formed on side surfaces of the second gateelectrode.
 8. The write-once memory device according to claim 5, furthercomprising sidewalls formed on side surfaces of each of the first gateelectrode and the second gate electrode.
 9. The write-once memory deviceaccording to claim 5, further comprising sidewalls formed on sidesurfaces of the third gate electrode.
 10. The write-once memory deviceaccording to claim 5, further comprising sidewalls formed on sidesurfaces of the fourth gate electrode.
 11. The write-once memory deviceaccording to claim 5, further comprising sidewalls formed on sidesurfaces of each of the third gate electrode and the fourth gateelectrode.
 12. The write-once memory device according to claim 5,further comprising sidewalls formed on side surfaces of each of thefirst gate electrode, the second gate electrode, the third gateelectrode, and the fourth gate electrode.